in the code below, how many artificial stages of delay should be inserted before the final instruction to avoid a data hazard?
movq %rdi , %rax
movq %rsi , %rcx
imulq %rcx , %rax

Respuesta :

In step 1, the first line will execute the first step, which fetches. Then in step 2, while line 1 is in the decode phase, line two will start fetching, and so on. The 3 lines of code will need to go through seven steps in order to complete all RISC pipeline for all three lines.

What is RISC pipeline  how can it be used to solve this problem?

In the early days of computer hardware, Reduced Instruction Set Computer Central Processing Units (RISC CPUs) was designed to execute one instruction per cycle, five stages in total. Those stages are, Fetch, Decode, Execute, Memory, and Write. The simplicity of operations performed allows every instruction to be completed in one processor cycle.

Fetch

In the Fetch stage, instruction is being fetched from the memory.

Decode

During the Decode stage, we decode the instruction and fetch the source operands

Execute

During the execute stage, the computer performs the operation specified by the instruction

Memory

If there is any data that needs to be accessed, it is done in the memory stage

Write

If we need to store the result in the destination location, it is done during the writeback stage,

Types of Code

There are five types of code we can write. We can write a load type, store type, branch, jump, or an R Type of code. Each type of code performs different stages of the RISC pipeline.

Load Type

Pipelines: Fetch, Decode, Execute, Memory, Write

R1 <- [1]

The above code is a Load Type. The address of 1 is getting loaded to R1. Load types consist of all five stages of the RISC pipeline. Load codes need to fetch, decode, execute, memory, and write to be completed.

Store Type

Pipeline: Fetch, Decode, Execute, Memory

[A] <- R1

The above code is a Store Type. R1 is getting stored in address A. Store type codes only need fetch, decode, execute and memory to be executed. We do not need to write.

Branch Type

Pipeline: Fetch, Decode, Execute

BNE R1, R2, Loop

The above code is a branch type. The code above checks if R1 is not equal to R2. If they are not equal, the code goes to Loop. If they are equal, it will not go to the loop.

Branch type codes need to fetch, decode and execute to run.

Jump

Pipeline: Fetch, Decode

JMP Loop

The above code is a JMP code. Jump is different than the branch type of code because Jump doesn’t check any conditional, it goes directly to the place stated in the code.

Jump types need to fetch and decode to run.

ALU — R Type

Pipeline: Fetch, Decode, Execute, Write

R1 <- R2 + R3

The above code is an ALU or an R Type. The operands, R2 and R3 are being added and stored in R1. This uses 4 stages of the pipeline, fetch, decode, execute, and write-only.

Code Example

Suppose we have the following 3 lines of code:

R1 <- [1]

R2 <- [2]

R3 <- [3]

In the code above, we are performing three load types. In line one, we are storing the address 1 to R1, line 2, we are storing address of 2 to R2 and finally in line 3, we are storing the address 3 to R3.

The RISC Pipeline will look something like this:

We know that Load Types execute all 5 stages of the RISC pipeline which again are, fetch, decode, execute, memory, and write.

To know more about RISC pipeline refer:

https://brainly.com/question/29220504

#SPJ4