Assuming the following system: Its page size is 256 bytes (instead of 4096 bytes). It uses 2-level page tables to perform virtual address translation. Its physical address space is 22-bit. It does not have a TLB. 1 PTE size Assuming each PTE only stores the physical frame number (PFN) and the valid/present bit. What would be the size of each PTE? Note that the size of the PTE must be a multiply of 8 bits (i.e., aligned to byte). 2 Virtual address space size Similar to x86, if we require each level of page table must fit into a physical page (i.e., its size is 256 bytes), what would be the virtual address space size? 3 Address translation Explain the steps involved in looking up the virtual address 0x3bf04d, when all involved pages are present in memory. 4 Page faults When accessing the above virtual address 0x3bf04d, where page fault may occur? Please answer all 4 questions